The present invention relates to a semiconductor device having high power and ultra-small bipolar transistors.
A side wall base contact structure (SICOS) is known and is such that it reduces the base-collector parasitic capacitance and improves the operating speed of a bipolar transistor. One example of the side wall base contact structure is shown in FIG. 1. The documents on such structure are, for example, JP-A-56-1556, USSN 443,554 filed Nov. 22, 1982 and JP-A-58-73156, which are incorporated herein by reference.
Referring to FIG. 1, reference number 1 represents a P-type silicon substrate, 2 an N.sup.+ -type buried layer, and 100 an insulator made of Si0.sub.2 film serving as element isolation or base-collector separation. Reference number 3 represents an N.sup.- -type collector region, 120 an N.sup.+ -type diffusion region for connection with the collector electrode, 19 a P-type base region, 150 a graft base region made of polycrystalline silicon film for connection with the base electrode, 20 an N.sup.+ -type emitter region, 21 a base electrode, 22 an emitter electrode, 23 a collector electrode, and 24 a line interconnecting the collector of a first transistor T.sub.1 and the base of a second transistor T.sub.2. In a known transistor structure shown in FIG. 1, the base electrode 21 is connected to the base region 19 by using the graft base region 150. Since the graft base region 150 is formed on a thick insulator 100, the base-collector parasitic capacitance becomes small and hence a high speed operation can be attained. In addition, since the graft base region 150 can be formed in a similar manner as of the interconnection layer, the degree of freedom in circuit layout increases to thereby enable the minituarization and high integration of integrated circuits.